A) Field of the Invention
The present invention relates to a semiconductor device having copper wirings and conductive plugs and its manufacture method.
B) Description of the Related Art
As LSI wiring material, copper (Cu) is now used which has a lower electric resistance and a higher electromigration resistance than aluminum (Al) used conventionally. A damascene method has generally been used for forming a Cu wiring, by which a Cu layer is deposited on an interlayer insulating film and filled in a recess formed in the film, and thereafter an unnecessary Cu layer is removed by chemical mechanical polishing (CMP). A single damascene method executes separately the process of filling a Cu layer in a via hole and CMP and the process of filling a Cu layer in a wiring groove and CMP. A dual damascene method executes the process of filling a Cu layer in a via hole and a wiring groove at the same time.
Japanese Patent Laid-open Publication No. 2000-173949 discloses a method of forming a Cu wiring by the damascene method. With this method, when a Cu layer is filled in a via hole or a wiring groove by an electrolytic plating method, a current/voltage supply method is altered during plating. For example, a d.c. plating is performed first and at an intermediate time a constant current plating is performed. By altering the current/voltage supply method, generation of voids can be suppressed.
By using Cu instead of Al conventionally used, an electromigration resistance of a wiring can be improved. A conventional Cu wiring forming method is, however, unsatisfactory in that a sufficient stressmigration resistance cannot be obtained in some cases.